After collecting information and searching stuff around I got the point I had ideas about what I was needing to run CP/M. First of all you need to be able to have RAM at address 0000H upwards second of course you need some kind of disk interface. Traditionally CP/M was designed to work with floppies, I still do have a 5 25" working disk unit and quite some floppies too but the problem was to find FDC controller chips, not easy.

Despite difficulties I managed to find a couple of chips, however while searching stuff around I found quite some information about IDE interfaces for Z80 systems and I though why not to try something a bit more ? Of course this meant I had to learn something about IDE and its protocol too.

There was another small problem, there was no way to fit all the components necessary in that board ( remember I was building all using plain simple TTL chips ) so first step was to add some kind of connector to allow me to add another board and put more chips in it, unfortunatelly owing to space constraints I had to put it in the location you see in the picture.

Next step was to create/test the ROM/RAM switcher, the circuit is very simple at RESET the FF is forced to switch to the ROM bank 0000-7FFFH, when it's changed via an OUT instruction it flips the bank into RAM. Half of that FF is used to divide by two the clock frequency and give a perfect 50% duty cycle.

Keep in mind that everything been done trying to re-use/use "at max" all the chips/gates already present on the board.

Next it was time to begin to make things getting a shape, the challenging part of course was testing so I decided to try a kind of modular approach building a small ( testable ) piece at time and test it before to proceed to mount the next one. Owing to the increased numbers of chips I had the idea to put buffers on all the lines, this turned out for various reasons a more complex situation than what initially forseen and also the source of some nasty bugs that took me months to figure out.